With the development of display technology, the flat panel device, such as Liquid Crystal Display (LCD) possesses advantages of high image quality, power saving, thin body and wide application scope. Thus, it has been widely applied in various consumer electrical products, such as mobile phone, television, personal digital assistant, digital camera, notebook, laptop, and becomes the major display device.
Most of the liquid crystal displays on the present market are back light type liquid crystal displays, which comprise a liquid crystal display panel and a back light module. The working principle of the liquid crystal display panel is to locate liquid crystal molecules between two parallel glass substrates, and a plurality of vertical and horizontal tiny electrical wires are between the two glass substrates. The light of back light module is reflected to generate images by applying driving voltages to control whether the liquid crystal molecules to be changed directions.
Generally, the liquid crystal display panel comprises a CF (Color Filter) substrate, a TFT (Thin Film Transistor) substrate, LC (Liquid Crystal) sandwiched between the CF substrate and TFT substrate and sealant. The formation process generally comprises: a forepart Array process (thin film, photo, etching and stripping), a middle Cell process (Lamination of the TFT substrate and the CF substrate) and a post module assembly process (Attachment of the driving IC and the printed circuit board). The forepart Array process is mainly to form the TFT substrate for controlling the movement of the liquid crystal molecules; the middle Cell process is mainly to add liquid crystal between the TFT substrate and the CF substrate; the post module assembly process is mainly the driving IC attachment and the integration of the printed circuit board. Thus, the liquid crystal molecules are driven to rotate and display pictures.
Low Temperature Poly Silicon (LTPS) is a kind of liquid crystal display technology which has been widely applied in the small, medium size electronic products. The electron mobility of the traditional amorphous silicon material is about 0.5-1.0 cm2/V·S but the electron mobility of the Low Temperature Poly Silicon can reach up to 30-300 cm2/V·S. Therefore, the Low Temperature Poly Silicon display has many advantages of high resolution, fast response speed and high aperture ratio.
However, on the other hand, the volume of the LTPS semiconductor element is small and the integration is high. The manufacture process of the entire LTPS array substrate is complicated, and the production cost is higher.
In the present manufacture process of the LTPS array substrate, the patterning of the polysilicon (Poly-si), the channel doping of the NMOS (Negative channel Metal Oxide Semiconductor) element and the N type heavy doping of the NMOS element (N+doping) respectively needs a mask, and the specific steps are:
as shown in FIG. 1, coating a photoresist layer 200 on the polysilicon layer, and after employing a first mask to implement exposure, development to the photoresist layer 200, and the remaining photoresist layer 200 is employed for shielding to etch the polysilicon layer to obtain a first polysilicon section 300 in the NMOS region and a second polysilicon section 400 in the PMOS (Positive channel Metal Oxide Semiconductor) region;
as shown in FIG. 2, coating a photoresist layer 500 on the on the first polysilicon section 300 and the second polysilicon section 400, and after employing a second mask to implement exposure, development to the photoresist layer 500, the second polysilicon section 400 of the PMOS region is shielded with the remaining photoresist layer 500, and implementing channel doping to the first polysilicon section 300;
as shown in FIG. 3, coating a photoresist layer 600 on the first polysilicon section 300 and the second polysilicon section 400, and after employing a second mask to implement exposure, development to the photoresist layer 600, the second polysilicon section 400 of the PMOS region and the middle region of the first polysilicon section 300 of the NMOS region are shielded with the remaining photoresist layer 600, and implementing N type heavy doping to two ends of the first polysilicon section 300.
The aforesaid manufacture processes require three masks for accomplishment. The process is complicated, and the production cost is high. Therefore, there is a need to provide a manufacture method of a Low Temperature Poly-silicon array substrate to solve the technical issue.